module top;

system_clock #6400  clock1(SEL);

system_clock #3200  clock2(A2);

system_clock #1600  clock3(A1); 

system_clock #800  clock4(A0);

system_clock #400  clock5(B2);

system_clock #200  clock6(B1);

system_clock #100  clock7(B0);

mux M1  (OUT1, OUT2, OUT3, A2, A1, A0, B2, B1, B0, SEL);

endmodule

module mux(OUT1, OUT2, OUT3, A2, A1, A0, B2, B1, B0, SEL);

output  OUT1, OUT2, OUT3;

input  A2, A1, A0, B2, B1, B0, SEL;

not n1(sel_n, SEL);

and a1(sel_A2, A2, SEL);

and a2(sel_A1, A1, SEL);

and a3(sel_A0, A0, SEL);

and a4(sel_B2, B2, sel_n);

and a5(sel_B1, B1, sel_n);

and a6(sel_B0, B0, sel_n);

or  b1(OUT1, sel_A2, sel_B2);

or  b2(OUT2, sel_A1, sel_B1);

or  b3(OUT3, sel_A0, sel_B0);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule