wire A1, B1, A0, B0, SEL, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT0;
system_clock #1600  clock1(A1);
system_clock #800  clock2(B1);
system_clock #400  clock3(A0);
system_clock #200  clock4(A0);
system_clock #100  clock5(SEL);
not a5(OUT5, SEL);
and a1(OUT6, A1, SEL);
and a2(OUT2, A0, SEL);
and a3(OUT3, SEL, B1);
and a4(OUT4, SEL, B0);
or  o1(OUT1, OUT3, OUT6);
or  o2(out0, OUT2, OUT4);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule