module top;

system_clock #6400  clock1(SEL);

system_clock #3200  clock2(A2);

system_clock #1600  clock3(A1); 

system_clock #800  clock4(A0);

system_clock #400  clock5(B2);

system_clock #200  clock6(B1);

system_clock #100  clock7(B0);

mux M1  (OUT1, OUT2, OUT3, A2, A1, A0, B2, B1, B0, SEL);

endmodule

module mux(OUT1, OUT2, OUT3, A2, A1, A0, B2, B1, B0, SEL);

output  OUT1, OUT2, OUT3;

input  A2, A1, A0, B2, B1, B0, SEL;

not n1(sel_n, SEL);

and a1(sel_A2, A2, SEL);

and a2(sel_A1, A1, SEL);

and a3(sel_A0, A0, SEL);

and a4(sel_B2, B2, sel_n);

and a5(sel_B1, B1, sel_n);

and a6(sel_B0, B0, sel_n);

or  b1(OUT1, sel_A2, sel_B2);

or  b2(OUT2, sel_A1, sel_B1);

or  b3(OUT3, sel_A0, sel_B0);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

module top; 

wire [3:0]OUT, A, B;

wire SEL;

system_clock #25600 clock1(SEL);

system_clock #12800 clock2(A[3]); 

system_clock #6400 clock3(A[2]); 

system_clock #3200 clock4(A[1]);

system_clock #1600 clock5(A[0]);

system_clock #800 clock6(B[3]);

system_clock #400 clock7(B[2]);

system_clock #200 clock8(B[1]);

system_clock #100 clock9(B[0]);

mux2 m1(OUT[1:0],A[1:0],B[1:0],SEL);

mux2 m2(OUT[3:2],A[3:2],B[3:2],SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

wire A1, B1, A0, B0, SEL, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT0;
system_clock #1600  clock1(A1);
system_clock #800  clock2(B1);
system_clock #400  clock3(A0);
system_clock #200  clock4(A0);
system_clock #100  clock5(SEL);
not a5(OUT5, SEL);
and a1(OUT6, A1, SEL);
and a2(OUT2, A0, SEL);
and a3(OUT3, SEL, B1);
and a4(OUT4, SEL, B0);
or  o1(OUT1, OUT3, OUT6);
or  o2(out0, OUT2, OUT4);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

我觉得这次自己做的很不错,因为有认真去学习,所以最后自己还是做了出来,其实也算是比较容易,没有很难